IMA Meeting on September 23, 2004 at
The AEC/APC XVI Symposium
Westin Hotel Denver, Colorado
Conference is September 18-23, 2004
IMA Meeting Registration available at -
click here

AEC/APC XVI Symposium
Registration is available at -
click here

IMA Meeting Agenda
at
AEC/APC Symposium XVI September 23, 2004

8:00 - 8:15 Introduction, John Pace
8:15 - 9:00 Standards Activity Review, Brad Van Eck
9:00 - 9:30 ITRS Update, James Moyne
9:30 - 9:50 IMA Survey, John Curry
9:50 - 10:05 Break
10:05 - 11:00 Featured Speaker, Fred Lewis Terry, Jr. (Abstract below) Metrology Challenges for End-of-Roadmap Nano-scale CMOS and Possible Post-CMOS Nanoelectronics
11:00 - 12:00 IMA Future Direction Discussions

Featured Speaker: Fred Lewis Terry, Jr. Department of Electrical Engineering and Computer Science University of Michigan, Ann Arbor, MI

Metrology Challenges for End-of-Roadmap Nano-scale CMOS and Possible Post-CMOS Nanoelectronics

As silicon CMOS is scaled into the sub-45 nm gate length regime, it will be necessary to modify the basic MOSFET device structure to maintain good electrical performance. A number of candidate device structures are being pursued in research labs. All of these present new challenges for metrology in general, and particularly strong challenges for in-line and integrated metrology for high-volume process control. For example, the FINFET, the Vertical Replacement Gate MOSFET, and other next generation device candidates require very critical control of active Si channel widths in the few nm-regime and place the gate insulator on sidewalls of the Si channel. Process "tricks" will permit the fabrication of these structures at sub-lithographic limit sizes, but measurement of key parameters such as the gate dielectric thickness become a lateral CD measurement issue and characterization of insulator/Si interfaces becomes even more difficult than with current planar structures.

The future beyond the end of Si CMOS scaling is far from clear, but a number of candidate device technologies are being pursued including carbon nanotubes and self-assembled molecular devices. No practical path to construction of large scale systems has yet emerged, but at least some of the metrology issues for a possible nanoelectronics manufacturing line can be anticipated.

In this talk, I will review some of these key measurement issues, look at what existing measurement systems will begin to fail, and, where I can, discuss possible solutions.